As semiconductor device dimensions have continued to shrink, it has become increasingly difficult to construct high yields of defect-free devices because of a number of challenges that have arisen in manufacturing these smaller devices. One such challenge is the production of interconnects. Due to the substantial decrease in device size, it has become progressively more difficult to maintain proper alignment of interconnect openings with targeted metal lines. Often, the pattern through which the interconnect opening is formed slightly misaligns with the underlying metal line. When conventional over-etch processes are conducted to insure that the dielectric layer is completely etched through to the metal line, the misaligned portion of the pattern will cause the etch to remove dielectric material along a lateral edge of the metal line. Thus, while a substantial portion of the opening lands on the intended metal line a small portion of the opening extends along a side edge of the metal line.
The misalignment of these interconnect openings is exacerbated by the fact that, as device sizes have continued to shrink, device aspect ratios and device densities have continued to increase. This causes an additional problem when forming the dielectric layer over such device topographies. Frequently, when dielectric materials are deposited, the high aspect ratios of the devices and their close proximity to each other prevents the dielectric material from uniformly depositing between the devices. As a result, voids can form adjacent the metal lines, and when the over-etch process is conducted, the etch can extend the opening to intersect with the void and extend across to another adjacent metal line, thereby creating a short when the opening is filled with metal.
Previous efforts to reduce short circuits due to via misalignment are not entirely satisfactory. Some efforts involve applying deposition processes, or using insulating materials with better void filling properties. Although some insulators are better void fillers than others, most insulating materials develop voids as design rules shrink. Moreover, the edge of the wafer is more susceptible to incomplete void filling than the center regardless of the deposition process used. In addition, an insulating material with little or no voids can have a higher capacitance than a void-containing insulating material. The use of an insulating material with a higher capacitance, in turn, will result in slower operating speeds for the semiconductor device.
Other ameliorative efforts have focused on decreasing the extent of misalignment between the via and the metal line. A certain degree of misalignment is inevitable, however, as design rule dimensions decrease to the resolution limits of photolithography. Misalignments can be corrected to some extent by reworking the semiconductor wafer. But reworking decreases the throughput of semiconductor device production, thereby increasing production costs. Furthermore, reworking can detrimentally alter the properties of the semiconductor wafer. For example, the chemical and plasma cleaning processes that are conducted to strip away photoresist can roughen the surface or alter the optical properties of the wafer, thereby detrimentally affecting the success of subsequent photolithographic processes.
Accordingly, what is needed in the art is a process for manufacturing interconnects in a semiconductor device that does not exhibit the limitations of the prior art.